1. Field of the Invention
This invention relates to a semiconductor memory, and more particularly to a semiconductor memory including insulated gate type field effect transistors (hereinafter abbreviated as FET) as memory elements.
2. Description of the Related Art
Among the semiconductor memories utilizing insulated gate type FETs as memory elements, there are known masked ROMs. Masked (or mask-programmed) ROMs are non-vola the memories into which information is permanently stored through the use of custom masks during fabrication. There are known NAND type ROMs and NOR type ROMs.
A NAND type ROM includes a series connection of a plurality of memory elements which are so made that all the memory elements can be turned on, and has an operation state where each individual memory element can be turned on or off according to the stored information and all the other memory elements are turned on. Usually, each memory element in a NAND type masked ROM determines the information "1" or"0" depending on whether the FET is depletion type or enhancement type.
A NOR type masked ROM includes a parallel connection of a plurality of memory elements. The individual memory element can be selectively driven into a read state to read out the stored information. Usually, a NOR type masked ROM determines the information "1" or "0" depending on whether the enhancement type FET has a low threshold voltage or a high threshold voltage. Sometimes, a NOR type masked ROM is called a high threshold voltage type ROM. In NOR Type masked ROM, an FET representing "0" does not become turned on in the operational state.
FIG. 12 shows an example of a NOR Type masked ROM circuit. Memory cells Mij formed of FETs are disposed in a matrix. Gate electrodes of the memory cell transistors belonging to the same row are connected to a common row line Ri, and drains of the memory cell transistors belonging to the same column are connected to a common column line Cj. The source electrode of each memory cell transistor is grounded. Each column line Cj is connected to a data out terminal D.sub.OUT through a transistor Tr which is controlled by a column decoder CD. The row line Ri is driven by a signal supplied from a row decoder RD.
Control signals P,r A.sub.0 -A.sub.3 are decoded in column decoder CD and row decoder RD to produce addressing signals. In the figure, those memory cells which are indicated by x are disconnected from the corresponding column line Cj. That is to say, even when the gate is applied with a drive voltage, the memory cell M does not become turned on. Specifically, the threshold voltage thereof is higher than the drive voltage, so that the memory does not allow a current to flow therethrough.
There is known such a method for manufacturing FETs of high threshold voltage in a NOR type masked ROM, as shown in FIGS. 13 and 14.
In FIG. 13, field oxide regions 11 are formed on a surface of a p-type semiconductor substrate 10 to define or surround active regions. On each active region, an insulated gate structure including a gate insulating film 12 and a gate electrode 14 is formed. Further, the surface of the gate electrode 14 is coated with an insulating film 16. For example, when the gate electrode 14 is made of polycrystalline silicon, the insulating film 16 can be made by oxidizing the surface of the gate electrode 14.
An n-type impurity ions such as P.sup.+ (phosphor) are implanted into the semiconductor substrate 10 utilizing the gate electrode structure 12, 14 and 16 and the field oxide 11 as a mask, to form ion implanted regions 18A and 20A between the gate electrode structure and the field oxide. The ion implanted region 18A corresponds to a source region and the other ion implanted region 20A corresponds to a drain region.
As shown in FIG. 14, a resist film 22 is coated on the substrate 10 and is patterned to have an aperture 22H by exposure and development. The resist mask 22 covers some of the FET structures and exposes gate structures and adjacent regions of some other FET structures formed on the same substrate. Then, boron ions B.sup.+ are accelerated at an accelerating voltage of about 120 KeV and implanted into the substrate 10 utilizing the gate structure 12, 14 and 16 and the resist mask 22 as an implantation mask.
This ion implantation is done to increase the acceptor concentration in the channel region below the gate electrode 14, thereby to increase the threshold voltage of the transistor. At the same time, boron impurity is also doped deep outside the gate structure and inside the aperture 22H below the ion implanted regions 18A and 20A. After the resist mask 22 is removed, the substrate is subjected to heat treatment which activates the implanted impurities. Thus, n.sup.+ -type source and drain regions 18 and 20 and a p-type impurity doped region 23 are provided.
The "cut-off" state of an FET necessary in a NOR type masked ROM, means that no current is allowed to flow through the source-drain current path even when a power source voltage (generally 5 V) is applied to the gate in the state where a voltage of 2 to 3 V is applied between the source and the drain.
In the above-described method, impurity ions are implanted through the gate electrode to the channel region to increase the p-type impurity concentration In the region 23 so as to set the threshold voltage of the FET higher than the power source voltage.
In case where the gate electrode 14 is formed of a polycide structure (a laminate structure of a lower polycrystalline silicon layer and an upper silicide layer), the ion implantation to the channel region is apt to be non-uniform due to the non-uniformity of the grains in the silicide layer. Thus, it is not easy to secure sufficient implantation dose in the channel.
Similar situation occurs also when the gate electrode 14 is made of a single layer structure of polycrystalline silicon, although the degree of non-uniformity is reduced. Therefore, there is a possibility that FETs having imperfect turn-off state may be generated, thereby decreasing the yield.
The region 23 doped with the p-type impurity extends from the channel region to the underside of the source and drain regions. Therefore, the capacitance of the pn-junctions between the p-type region 23 and the n.sup.+ -type source and drain regions 18 and 20 become large to decrease the operation speed of the circuit.